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NB3N502 14 MHz to 190 MHz PLL Clock Multiplier
Description
The NB3N502 is a clock multiplier device that generates a low jitter, TTL/CMOS level output clock which is a precise multiple of the external input reference clock signal source. The device is a cost efficient replacement for the crystal oscillators commonly used in electronic systems. It accepts a standard fundamental mode crystal or an external reference clock signal. Phase-Locked-Loop (PLL) design techniques are used to produce an output clock up to 190 MHz with a 50% duty cycle. The NB3N502 can be programmed via two select inputs (S0, S1) to provide an output clock (CLKOUT) at one of six different multiples of the input frequency source, and at the same time output the input aligned reference clock signal (REF).
Features
http://onsemi.com MARKING DIAGRAM
8 1 SOIC-8 D SUFFIX CASE 751 3N502 A L Y W G 8 3N502 ALYW G 1 = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
* * * * * * * * * * *
Clock Output Frequency up to 190 MHz Operating Range: VDD = 3 V to 5.5 V Low Jitter Output of 15 ps One Sigma (rms) Zero ppm Clock Multiplication Error 45% - 55% Duty Cycle 25 mA TTL-level Drive Outputs Crystal Reference Input Range of 5 - 27 MHz Input Clock Frequency Range of 2 - 50 MHz Available in 8-pin SOIC Package or in Die Form Full Industrial Temperature Range -40C to 85C This is a Pb-Free Device
VDD
ORDERING INFORMATION
Device NB3N502DG NB3N502DR2G Package SOIC-8 (Pb-Free) SOIC-8 (Pb-Free) Shipping 98 Units/Rail 2500/Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
Reference Clock
TTL/ CMOS Output
REF
X1/CLK X2
Crystal Oscillator Multiplier Select
/P
Phase Detector
Charge Pump
VCO
TTL/ CMOS Output
CLKOUT
/M S1 S0 GND
Feedback
Figure 1. NB3N502 Logic Diagram
(c) Semiconductor Components Industries, LLC, 2006
1
March, 2006 - Rev. 0
Publication Order Number: NB3N502/D
NB3N502
X1/CLK VDD GND REF
1
8 7 6 5
X2
2 3 4
S1 S0 CLKOUT
Figure 2. Pin Configuration (Top View)
Table 1. CLOCK MULTIPLIER SELECT TABLE
S1* L L M M H H S0** L H L H L H Multiplier 2X 5X 3X 3.33X 4X 2.5X
L = GND H = VDD M = OPEN (unconnected) * Pin S1 defaults to M when left open ** Pin S0 defaults to H when left open
Table 2. OUTPUT FREQUENCY EXAMPLES
Output Frequency (MHz) Input Frequency (MHz) S1, S0 20 10 0 ,0 25 10 1, 1 33.3 10 M, 1 48 16 M, 0 50 20 1, 1 54 13.5 1, 0 64 16 1, 0 66.66 20 M, 1 75 15 0, 1 100 20 0, 1 108 27 1, 0 120 24 0, 1 135 27 0, 1
Table 3. PIN DESCRIPTION
Pin # 1 2 3 4 5 6 7 8 Name X1/CLK VDD GND REF CLKOUT S0 S1 X2 I/O Input Power Supply Power Supply CMOS/TTL Output CMOS/TTL Output CMOS/TTL Input Three-level Input Crystal Input Description Crystal or External Reference Clock Input Positive Supply Voltage (3 V to 5.5 V) 0 V Ground. Buffered Crystal Oscillator Clock Output Clock Output Multiplier Select Pin - Connect to VDD or GND. Internal Pull-up Resistor. Multiplier Select Pin - Connect to VDD, GND or Float to M. Crystal Input - Do Not Connect when Providing an External Clock Reference
Table 4. ATTRIBUTES
Characteristic ESD Protection Human Body Model Machine Model Value > 8 kV > 600 V Level 1 UL 94 V-0 @ 0.125 in 6700 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test Oxygen Index: 28 to 34
1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
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NB3N502
Table 5. MAXIMUM RATINGS
Symbol VDD VI TA Tstg qJA qJC Parameter Positive Power Supply Input Voltage Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) 0 LFPM 500 LFPM (Note 1) SOIC-8 SOIC-8 SOIC-8 Condition 1 GND = 0 V Condition 2 Rating 7 GND - 0.5 = VI = VDD + 0.5 -40 to +85 -65 to +150 190 130 41 to 44 Units V V C C C/W C/W C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. JEDEC standard multilayer board - 2S2P (2 signal, 2 power).
Table 6. DC CHARACTERISTICS (VDD = 3 V to 5.5 V unless otherwise noted, GND = 0 V, TA = -40C to +85C) (Note 2)
Symbol IDD VOH VOL VIH VIL VIH VIL VIM Cin ISC Characteristic Power Supply Current (unloaded CLKOUT operating at 100 MHz with 20 MHz crystal) Output HIGH Voltage Output LOW Voltage IOH = -25 mA TTL High IOL = 25 mA (VDD / 2) + 1 VDD / 2 VDD / 2 VDD - 0.5 0.5 VDD / 2 4 70 (VDD / 2) -1 2.4 0.4 Min Typ 20 Max Unit mA V V V V V V V pF mA
Input HIGH Voltage, CLK only (pin 1) Input LOW Voltage, CLK only (pin 1) Input HIGH Voltage, S0, S1 Input LOW Voltage, S0, S1 Input level of S1 when open (Input Mid Point) Input Capacitance, S0, S1 Output Short Circuit Current
2. Parameters are guaranteed by characterization and design, not tested in production.
Table 7. AC CHARACTERISTICS (VDD = 3 V to 5.5 V unless otherwise noted, GND = 0 V, TA = -40C to +85C) (Note 3)
Symbol fXtal fCLK fOUT Crystal Input Frequency Clock Input Frequency Output Frequency Range VDD = 4.5 to 5.5 V (5.0 V 10%) VDD = 3.0 to 3.6 V (3.3 V 10%) Clock Output Duty Cycle at 1.5 V up to 190 MHz Period Jitter (RMS, 1 ) Total Period Jitter, (peak-to-peak) Output rise/fall time (0.8 V to 2.0 V / 2.0 V to 0.8 V) Characteristic Min 5 2 14 14 45 50 15 40 1 Typ Max 27 50 190 120 55 Unit MHz MHz MHz MHz % ps ps ns
DC tjitter (rms) tjitter (pk-to-pk) tr/tf
3. Parameters are guaranteed by characterization and design, not tested in production.
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NB3N502
APPLICATIONS INFORMATION
High Frequency CMOS/TTL Oscillators Series Termination Resistor Recommendation
The NB3N502, along with a low frequency fundamental mode crystal, can build a high frequency CMOS/TTL output oscillator. For example, a 20 MHz crystal connected to the NB3N502 with the 5X output selected (S1 = L, S0 = H) produces a 100 MHz CMOS/TTL output clock. External Components
Decoupling Instructions
A 33 W series terminating resistor can be used on the CLKOUT pin.
Crystal Load Capacitors Selection Guide
In order to isolate the NB3N502 from system power supply, noise de-coupling is required. The 0.01 mF decoupling capacitor has to be connected between VDD and GND on pins 2 and 3. It is recommended to place de-coupling capacitors as close as possible to the NB3N502 device to minimize lead inductance. Control input pins can be connected to device pins VDD or GND, or to the VDD and GND planes on the board.
The total on-chip capacitance is approximately 12 pF per pin (CIN1 and CIN2). A parallel resonant, fundamental mode crystal should be used. The device crystal connections should include pads for small capacitors from X1/CLK to ground and from X2 to ground. These capacitors, CL1 and CL2, are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance (CLOAD (crystal)). Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) between the crystal and device. Crystal load capacitors, if needed, must be connected from each of the pins X1 and X2 to ground. The load capacitance of the crystal (CLOAD (crystal)) must be matched by total load capacitance of the oscillator circuitry network, CINX, CSX and CLX, as seen by the crystal (see Figure 3 and equations below).
Internal to Device
R G
CLOAD1 = CIN1 + CS1 + CL1 [Total capacitance on X1/CLK] CLOAD2 = CIN2 + CS2 + CL2 [Total capacitance on X2] CIN1 [ CIN2 [ 12 pF (Typ) [Internal capacitance] CS1 [ CS2 [ 5 pF (Typ) [External PCB stray capacitance] CLOAD1,2 = 2 S CLOAD (Crystal) CL2 = CLOAD2 - CIN2 - CS2 [External load capacitance on X2] CL1 = CLOAD1 - CIN1 - CS1 [External load capacitance on X1/CLK] CIN2 12 pF
CIN1 12 pF
X1/CLK CS1 CS2
X2
Example 1: Equal stray capacitance on PCB CLOAD (Crystal) = 18 pF (Specified by the crystal manufacturer) CLOAD1 = CLOAD2 = 36 pF CIN1 = CIN2 = 12 pF CS1 = CS2 = 6 pF CL1 = 36 - 12 - 6 = 18 pF CL2 = 36 - 12 - 6 = 18 pF Example 2: Different stray capacitance on PCB trace X1/CLK vs. X2 CLOAD (Crystal) = 18 pF CLOAD1 = CLOAD2 = 36 pF CIN1 = CIN2 = 12 pF CS1 = 4 pF & CS2 = 8 pF CL1 = 36 - 12 - 4 = 20 pF CL2 = 36 - 12 - 8 = 16 pF
CL1
CL2
Crystal
Figure 3. Using a Crystal as Reference Clock
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NB3N502
PACKAGE DIMENSIONS
SOIC-8 NB CASE 751-07 ISSUE AH
A
8 5
-X-
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
SOLDERING FOOTPRINT*
1.52 0.060
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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NB3N502/D

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